1. Field of the Invention
The field of the invention relates generally to methods and apparatus for performing numerical calculations, and more particularly to methods and apparatus for obtaining the multiplicative negate of a product of two numbers.
2. Background
Circuits often implement basic mathematic operations, such as addition, multiplication and negation, to perform numeric calculations. Typically, the greater the number of separate mathematical operations involved in a numeric calculation, the more time a circuit will use to perform the calculation. Accordingly, decreasing the number of separate operations used can improve calculation speed. Such performance improvements can be particularly noticeable in circuits that perform large numbers of calculations, such as digital signal processing functions or matrix multiplication for multimedia applications, for example.
A particular numeric calculation performed by some digital circuits is the multiply/subtract calculation which generates the difference A-(B*C). To perform this calculation, conventional digital circuits may (i) generate the product B*C of two numbers, a multiplicand B and multiplier C, (ii) negate this product to obtain the multiplicative negate product -B*C, and (iii) add this multiplicative negate product to the third number, A. As can be seen, this conventional multiply/subtract calculation uses three separate operations. In particular, it produces the difference A-(B*C) by performing, first, the multiply operation to obtain the product B*C; second, the negate operation to obtain the multiplicative negate -B*C; and, third, the add operation to obtain the difference A-B*C. Because each of these separate operations typically consumes time, reducing the number of such separate operations might improve the speed of methods and apparatus that perform this multiply/subtract calculation.
Another type of calculation performed by digital circuits, the multiply/add calculation, produces the sum A+(B*C). Because this multiply/add calculation does not involve the "subtract" used in the multiply/subtract calculation, it eliminates the separate negate operation used in the multiply/subtract. In particular, a conventional multiply/add circuit may use only two separate operations, the multiply operation and the add operation, to produce the sum A+(B*C).
For cost, space or other reasons, conventional digital circuits may attempt to use common circuitry to perform both the multiply/add and the multiply/subtract calculations. Unfortunately, the different number of operations used by the multiply/add and the multiply/subtract can complicate the use of such common circuitry. For example, common multiply/add and multiply/subtract circuitry may require additional control or other circuitry to account for timing differences and to account for the different operations performed by the multiply/add and multiply/subtract. This additional circuitry may require additional design and testing and may use additional area on the semiconductor die.
Accordingly, there has been a need for a method and apparatus that performs a multiply/subtract calculation using a reduced number of separate operations. Such a multiply/subtract method and apparatus may perform a multiply/subtract more rapidly than conventional multiply/subtract circuits and using no more than the number of separate operations used by a conventional multiply/add circuit. Such a multiply/subtract method and apparatus might reduce the semiconductor area used to implement multiply/subtract circuits or to implement integrated multiply/subtract and multiply/add circuits. Such a multiply/subtract method and apparatus might eliminate additional design and testing associated with integrating such circuits.